1. Field of the Invention
This invention relates generally to systems for verifying an architecture, and more particularly to techniques for hardware verification in multiprocessor (“MP”) computer systems.
2. Description of the Related Art
An important aspect of designing an advanced computer processor is the ability to test the design of the processor thoroughly, in order to assure that the design complies with desired architectural, performance and design specifications. One known verification technique requires the generation of a large number of instruction sequences to assure that the processor behaves properly under a wide variety of circumstances.
Test program generators are basically sophisticated software engines, which are used to create numerous hard-coded test cases. By appropriate configuration, it is possible for test generation to be focused on very specific ranges of conditions, or broadened to cover a wide range of logic. Today, large numbers of test cases can be created in the time that a single test case could be written manually, as was done prior to the advent of test case generators. Modern test program generators are sophisticated enough to evaluate the microarchitectural implementation of a processor.
Typically, the input to the test program generator is a user defined sequence of partially specified instructions, known as the instruction stream, which acts as a template for the test to be generated. The instruction stream is generally incomplete, in that various details of each instruction, such as the specific source and the target resources to be used, the data values of each uninitialized resource, and even the exact instruction to be generated, may be left unspecified. The test program generator then generates a complete test by filling in the missing information with random values. The choice of random values is often biased, so as to increase the likelihood of detecting a design flaw. The use of templates in this manner allows the creation of numerous test cases that stress the implementation of the logic, creating various conditions such as “buffer full,” “pipe stall”.
An example of a conventional test program generator is the IBM tool, “Genesys”, which is disclosed in the document Model-Based Test Generation for Process Design Verification, Y. Lichtenstein et. al., Sixth Innovative Applications of Artificial Intelligence Conference, August 1994, pp. 83-94.
Another conventional test program generator, AVPGEN, is disclosed in the document AVPGEN—A Generator for Architecture Verification Test Cases, A. Chandra, et al. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 3, No. 2, 188-200 (June 1995).
Verification of multiprocessor designs present special complexities, because of race conditions that can occur in different registers and other memory stores, such that results are unpredictable and non-unique.
A test generator is disclosed in the publication B. O'Krafka, et al., “MPTG: A Portable Test Generator for Cache-Coherent Multiprocessors”, International Conference on Computers and Communications, 1995, pp 38-44. This generator is capable of generating tests that include scenarios with unpredictable results and relies on checks carried out for intermediate points in the test. These checks are done while the test is simulated on the design simulator. It operates without reference to predicted architectural results in the test itself. This generator is limited in the types of collision scenarios that can be generated and in the types of violations that can be detected via these checks.